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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a OP181/op281/op481 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996 ultralow power, rail-to-rail output operational amplifiers pin configurations features low supply current: 4 m a/amplifier max single-supply operation: 2.7 v to 12 v wide input voltage range rail-to-rail output swing low offset voltage: 1.5 mv no phase reversal applications comparator battery powered instrumentation safety monitoring remote sensors low voltage strain gage amplifiers general description the OP181, op281 and op481 are single, dual and quad ultralow power, single-supply amplifiers featuring rail-to-rail outputs. all operate from supplies as low as 2.0 v and are specified at +3 v and +5 v single supply as well as 5 v dual supplies. fabricated on analog devices cbcmos process, the OP181 family features a precision bipolar input and an output that swings to within millivolts of the supplies and continues to sink or source current all the way to the supplies. applications for these amplifiers include safety monitoring, portable equipment, battery and power supply control, and signal conditioning and interface for transducers in very low power systems. the outputs ability to swing rail-to-rail and not increase supply current, when the output is driven to a supply voltage, enables the OP181 family to be used as comparators in very low power systems. this is enhanced by their fast saturation recovery time. propagation delays are 250 m s. the OP181/op281/op481 are specified over the extended industrial (C40 c to +85 c) temperature range. the OP181, single, and op281, dual, amplifiers are available in 8-pin plastic dips and so surface mount packages. the op281 is also available in 8-lead tssop. the op481 quad is available in 14- pin dips, narrow 14-pin so and tssop packages. nc = no connect 8 7 6 5 1 2 3 4 null v+ null nc out a ?n a +in a v OP181 nc = no connect null v+ null nc out a ?n a +in a v 1 4 5 8 OP181 8-lead so 8-lead epoxy dip (s suffix) (p suffix) 8 7 6 5 1 2 3 4 op281 out a v+ +in b ?n b out b ?n a +in a v out a v+ out b ?n a +in a v +in b ?n b 1 4 5 8 op281 8-lead so 8-lead epoxy dip (s suffix) (p suffix) 14-lead epoxy dip 14-lead (p suffix) narrow-body so (s suffix) 8-lead tssop (ru suffix) op281 1 4 5 8 14 13 12 11 10 9 8 1 2 3 4 7 6 5 out a v +in d ?n d out d ?n a +in a v+ out c ?n c +in c +in b ?n b out b op481 1 7 8 14 op481 14-lead tssop (ru suffix) op481 1 78 14 note: pin orientation is equivalent for each package variation
C2C rev. 0 OP181/op281/op481Cspecifications electrical specifications parameter symbol conditions min typ max units input characteristics offset voltage v os note 1 1.5 mv C40 c t a +85 c 2.5 mv input bias current i b C40 c t a +85 c310na input offset current i os C40 c t a +85 c 0.1 7 na input voltage range 0 2 v common-mode rejection ratio cmrr v cm = 0 v to 2.0 v, C40 c t a +85 c6595 db large signal voltage gain a vo r l = 1 m w , v o = 0.3 v to 2.7 v 5 13 v/mv C40 c t a +85 c 2 v/mv offset voltage drift d v os / d t10 m v/ c bias current drift d i b / d t 20 pa/ c offset current drift d i os / d t 2 pa/ c output characteristics output voltage high v oh r l = 100 k w to gnd, C40 c t a +85 c 2.925 2.96 v output voltage low v ol r l = 100 k w to v+, C40 c t a +85 c2575mv short circuit limit i sc 1.1 ma power supply power supply rejection ratio psrr v s = 2.7 v to 12 v C40 c t a +85 c7695 db supply current/amplifier i sy v o = 0 v 3 4 m a C40 c t a +85 c5 m a dynamic performance slew rate sr r l = 100 k w , c l = 50 pf 25 v/ms turn on time a v = 1, v o = 1 40 m s turn on time a v = 20, v o = 1 50 m s saturation recovery time 65 m s gain bandwidth product gbp 95 khz phase margin f o 70 degrees noise performance voltage noise e n p-p 0.1 hz to 10 hz 10 m v p-p voltage noise density e n f = 1 khz 75 nv/ ? hz current noise density i n <1 pa/ ? hz notes 1 v os is tested under no load condition. specifications subject to change without notice. (@ v s = +3.0 v, v cm = 1.5 v, t a = +25 8 c unless otherwise noted)
C3C rev. 0 OP181/op281/op481 electrical specifications parameter symbol conditions min typ max units input characteristics offset voltage v os note 1 0.1 1.5 mv C40 c t a +85 c 2.5 mv input bias current i b C40 c t a +85 c310na input offset current i os C40 c t a +85 c 0.1 7 na input voltage range 0 4 v common-mode rejection ratio cmrr v cm = 0 v to 4.0 v, C40 c t a +85 c6590 db large signal voltage gain a vo r l = 1 m w , v o = 0.5 v to 4.5 v 5 15 v/mv C40 c t a +85 c 2 v/mv offset voltage drift d v os / d t C40 c to +85 c10 m v/ c bias current drift d i b / d t20pa/ c offset current drift d i os / d t2pa/ c output characteristics output voltage high v oh r l = 100 k w to gnd, C40 c t a +85 c 4.925 4.96 v output voltage low v ol r l = 100 k w to v+, C40 c t a +85 c2575mv short circuit limit i sc 3.5 ma power supply power supply rejection ratio psrr v s = 2.7 v to 12 v, C40 c t a +85 c7695 db supply current/amplifier i sy v o = 0 v 3.2 4 m a C40 c t a +85 c5 m a dynamic performance slew rate sr r l = 100 k w , c l = 50 pf 27 v/ms saturation recovery time 120 m s gain bandwidth product gbp 100 khz phase margin f o 74 degrees noise performance voltage noise e n p-p 0.1 hz to 10 hz 10 m v p-p voltage noise density e n f = 1 khz 75 nv/ ? hz current noise density i n <1 pa/ ? hz notes 1 v os is tested under a no load condition. specifications subject to change without notice. (@ v s = +5.0 v, v cm = 2.5 v, t a = +25 8 c unless otherwise noted 1 )
C4C rev. 0 OP181/op281/op481Cspecifications electrical specifications parameter symbol conditions min typ max units input characteristics offset voltage v os note 1 0.1 1.5 mv C40 c t a +85 c 2.5 mv input bias current i b C40 c t a +85 c310na input offset current i os C40 c t a +85 c 0.1 7 na input voltage range C5 +4 v common-mode rejection cmrr v cm = C5.0 v to +4.0 v, C40 c t a +85 c6595db large signal voltage gain a vo r l = 1 m w , v o = 4.0 v, 5 13 v/mv C40 c t a +85 c 2 v/mv offset voltage drift d v os / d t C40 c to +85 c10 m v/ c bias current drift d i b / d t 20 pa/ c offset current drift d i os / d t 2 pa/ c output characteristics output voltage swing v o r l = 100 k w to gnd, C40 c t a +85 c 4.925 4.98 v short circuit limit i sc 12 ma power supply power supply rejection ratio psrr v s = 1.35 v to 6v, C40 c t a +85 c7695db supply current/amplifier i sy v o = 0 v 3.3 5 m a C40 c t a +85 c6 m a dynamic performance slew rate sr r l = 100 k w , c l = 50 pf 28 v/ms gain bandwidth product gbp 105 khz phase margin f o 75 degrees noise performance voltage noise e n p-p 0.1 hz to 10 hz 10 m v p-p voltage noise density e n f = 1 khz 85 nv/ ? hz voltage noise density e n f = 10 khz 75 nv/ ? hz current noise density i n <1 pa/ ? hz notes 1 v os is tested under no load condition. specifications subject to change without notice. (@ v s = 5 v, t a = +25 8 c unless otherwise noted)
OP181/op281/op481 C5C rev. 0 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the OP181/op281/op481 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precau- tions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 v input voltage . . . . . . . . . . . . . . . . . . . . . . . . gnd to v s + 10 v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 3.5 v output short-circuit duration to gnd . . . . . . . . . . indefinite storage temperature range p, s, ru package . . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature range OP181/op281/op481g . . . . . . . . . . . . . . . C40 c to +85 c junction temperature range p, s, ru package . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . +300 c package type u ja * u jc units 8-pin plastic dip (p) 103 43 c/w 8-pin soic (s) 158 43 c/w 8-pin tssop (ru) 240 43 c/w 14-pin plastic dip (p) 76 33 c/w 14-pin soic (s) 120 36 c/w 14-pin tssop (ru) 240 43 c/w * q ja is specified for the worst case conditions, i.e., q ja is specified for device in socket for p-dip packages; q ja is specified for device soldered in circuit board for tssop and soic packages. ordering guide temperature package package model range description option OP181gp C40 c to +85 c 8-pin plastic dip n-8 OP181gs C40 c to +85 c 8-pin soic so-8 op281gp C40 c to +85 c 8-pin plastic dip n-8 op281gs C40 c to +85 c 8-pin soic so-8 op281gru C40 c to +85 c 8-pin tssop ru-8 op481gp C40 c to +85 c 14-pin plastic dip n-14 op481gs C40 c to +85 c 14-pin soic so-14 op481gru C40 c to +85 c 14-pin tssop ru-14
?.0 ?.8 ?.6 ?.4 ?.2 0 0.2 0.4 0.6 0.8 1.0 input offset voltage ?mv quantity ?amplifiers 45 40 0 20 15 10 5 35 25 30 v s = +2.7v t a = +25 8 c figure 1. input offset voltage distribution temperature ? 8 c 0 ?.5 ?.0 ?0 20 0 2040 6080 ?.5 ?.0 ?.0 ?.5 ?.0 ?.0 ?.5 ?.5 100 120 input bias current ?na v s = +5v figure 4. input bias current vs. temperature load current ?? output voltage ?mv 10,000 1,000 0.1 1 1000 10 100 100 10 1.0 source sink v s = +3v t a = +25 8 c figure 7. output voltage to supply rail vs. load current rev. 0 OP181/op281/op481Ctypical characteristics C6C input offset voltage ?mv ?.0 ?.8 ?.6 ?.4 ?.2 0 0.2 0.4 0.6 0.8 1.0 quantity ?amplifiers 45 40 0 20 15 10 5 35 25 30 v s = +5v t a = +25 8 c 50 figure 2. input offset voltage distribution common-mode voltage ?volts input bias current ?na 1.0 ?.0 ?.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 ?.5 ?.5 ?.0 0.5 ?.5 0.0 ?.0 3.5 4.0 v s = +5v t a = +25 8 c 4.5 5.0 figure 5. input bias current vs. common-mode voltage load current ?? output voltage ?mv 1,000 0.1 1 1000 10 100 100 10 1.0 source sink v s = +5v t a = +25 8 c figure 8. output voltage to supply rail vs. load current temperature ? 8 c input offset voltage ?? 2000 600 0 ?0 20 0 2040 6080 1800 800 400 200 1600 1200 1400 1000 100 120 v s = +5v figure 3. input offset voltage vs. temperature temperature ? 8 c input offset current ?na 0.5 ?.1 ?.4 ?0 ?0 0 20 40 60 80 0 ?.2 ?.3 0.4 0.2 0.3 0.1 100 120 v s = +5v figure 6. input offset current vs. temperature load current ?? output voltage ?mv 1,000 0.1 1 1000 10 100 100 10 1.0 source sink v s = 5v t a = +25 8 c figure 9. output voltage to supply rail vs. load current
OP181/op281/op481 C7C rev. 0 frequency ?hz open-loop gain ?db 70 60 ?0 100 1k 1m 10k 100k 20 50 40 30 10 0 ?0 ?0 v s = +5v t a = +25 8 c r l = 100k w 90 0 45 135 180 225 270 phase shift ?degrees figure 10. open-loop gain and phase vs. frequency frequency ?hz open-loop gain ?db 70 60 ?0 100 1k 1m 10k 100k 20 50 40 30 10 0 ?0 ?0 v s = 5v t a = +25 8 c r l = 100k w to ground 90 0 45 135 180 225 270 phase shift ?degrees figure 13. open-loop gain and phase vs. frequency frequency ?hz cmrr ?db 1k 10k 10m 100k 1m 90 80 ?0 70 60 50 40 30 20 10 0 t a = +25 8 c v s = 5v v s = +5v v s = +3v figure 16. cmrr vs. frequency frequency ?hz open-loop gain ?db 70 60 ?0 100 1k 1m 10k 100k 20 50 40 30 10 0 ?0 ?0 v s = +2.7v t a = +25 8 c r l = 100k w 90 0 45 135 180 225 270 phase shift ?degrees figure 12. open-loop gain and phase vs. frequency frequency ?hz v s = +5v t a = +25 8 c marker @ 67nv/ ? hz 0 2k4k6k8k10k 50nv/ ? hz/ div figure 15. voltage noise density vs. frequency capacitance ?pf small signal overshoot ?% 50 45 0 10 100 1000 40 35 30 25 20 15 10 5 v s = +5v v in = 50mv r l = 100k w t a = +25 8 c ?s +os figure 18. small signal overshoot vs. load capacitance frequency ?hz open-loop gain ?db 70 60 ?0 100 1k 1m 10k 100k 20 50 40 30 10 0 ?0 ?0 v s = +3v t a = +25 8 c r l = 100k w 90 0 45 135 180 225 270 phase shift ?degrees figure 11. open-loop gain and phase vs. frequency frequency ?hz closed-loop gain ?db 10 100 1m 1k 10k 100k 60 50 ?0 40 30 20 10 0 ?0 ?0 ?0 v s = +5v t a = +25 8 c r l = infinite figure 14. closed-loop gain vs. frequency frequency ?hz psrr ?db 10 100 1m 1k 10k 100k 160 140 ?0 120 100 80 60 40 20 0 ?0 v s = 5v, +5v, +3v, +2.7v t a = +25 8 c r l = infinite figure 17. psrr vs. frequency
OP181/op281/op481 C8C rev. 0 frequency ?hz 5 4 0 10 100 100k 1k 10k 3 2 1 maximum output swing ?vp-p v s = +5v v in = 4vp? r l = infinite t a = +25 8 c figure 19. maximum output swing vs. frequency temperature ? 8 c supply current/amplifier ?? 4.5 1.5 0 ?0 ?0 0 20 40 60 80 100 120 3.5 2.0 1.0 0.5 3.0 2.5 v s = +5v 4.0 figure 22. supply current/amplifier vs. temperature 10 0% 100 90 0mv a2 100? 50mv v s = 1.35v a v = 1 r l = 100k w c l = 50pf t a = +25 8 c figure 25. small signal transient response temperature ? 8 c supply current/amplifier ?? 4.0 1.5 0 ?0 ?0 0 20 40 60 80 100 120 3.5 2.0 1.0 0.5 3.0 2.5 v s = +3v figure 21. supply current/amplifier vs. temperature 10 0% 100 90 0mv a2 100? 50mv v s = 2.5v a v = 1 r l = 100k w c l = 50pf t a = +25 8 c figure 24. small signal transient response 10 0% 100 90 0.50v a2 100? 500mv v s = +2.7v a v = 1 r l = 100k w c l = 50pf t a = +25 8 c figure 27. large signal transient response frequency ?hz 3 0 10 100 100k 1k 10k 2 1 maximum output swing ?vp-p v s = +3v v in = 2vp? r l = infinite t a = +25 8 c figure 20. maximum output swing vs. frequency supply voltage ? volts supply current/amplifier ?? 3.50 2.00 0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.00 2.25 1.75 1.50 2.75 2.50 t a = +25 8 c 3.25 0.75 1.00 0.50 0.25 1.25 4.5 5.0 5.5 6.0 figure 23. supply current/amplifier vs. supply voltage 10 0% 100 90 2.50v a2 100? 1v v s = +5v a v = 1 r l = 100k w c l = 50pf t a = +25 8 c figure 26. large signal transient response
OP181/op281/op481 C9C rev. 0 10 0% 100 90 2.50v a2 200? 1v v s = +5v t a = +25 8 c 1v figure 28. no phase reversal 10 0% 100 90 0.00v a2 50? 500mv v s = 6 1.35v r l = 500mv v in = 6 1vp-p at 2khz figure 30. saturation recovery time frequency ?hz channel separation ?db 100 1k 1m 10k 100k 120 105 ?0 90 75 60 45 30 15 0 ?5 v s = +5v t a = +25 8 c r l = figure 29. channel separation vs. frequency 10 0% 100 90 0.00v a2 100? 1v v s = 6 2.5v circuit = a vol 500mv r l = t a = +25 8 c figure 31. saturation recovery time
OP181/op281/op481 C10C rev. 0 applications theory of operation the opx81 family of op amps is comprised of extremely low powered, rail-to-rail output amplifiers, requiring less than 4 m a of quiescent current per amplifier. many other competitors devices may be advertised as low supply current amplifiers but draw significantly more current as the outputs of these devices are driven to a supply rail. the opx81s supply current remains under 4 m a even with the output driven to either supply rail. supply currents should meet the specification as long as the inputs and outputs remain within the range of the power supplies. figure 32 shows a simplified schematic of the OP181. a bipolar differential pair is used in the input stage. pnp transistors are used to allow the input stage to remain linear with the common- mode range extending to ground. this is an important consider- ation for single supply applications. the bipolar front end also contributes less noise than a mos front end with only nano- amps of bias currents. the output of the op amp consists of a pair of cmos transistors in a common source configuration. this setup allows the output of the amplifier to swing to within millivolts of either supply rail. the headroom required by the output stage is limited by the amount of current being driven into the load. the lower the output current, the closer the output can go to either supply rail. figures 7, 8 and 9 show the output voltage headroom versus load current. this behavior is typical of rail-to-rail output amplifiers. +in ?n v ee out v cc figure 32. simplified schematic of the OP181 input overvoltage protection the input stage to the opx81 family of op amps consists of a pnp differential pair. if the base voltage of either of these input transistors drops to more than 0.6 v below the negative supply, the input esd protection diodes will become forward biased, and large currents will begin to flow. in addition to possibly damaging the device, this will create a phase reversal effect at the output. to prevent these effects from happening, the input current should be limited to less than 0.5 ma. this can be done quite easily by placing a resistor in series with the input to the device. the size of the resistor should be pro- portional to the lowest possible input signal excursion and can be found using the following formula: r = v ee - v in , min 0.5 10 - 3 where: v ee is the negative power supply for the amplifier, and v in, min is the lowest input voltage excursion expected for example, an OP181 is to be used with a single supply volt- age of 5 v where the input signal could possibly go as low as C1.0 v. because the amplifier is powered from a single supply, v ee is ground, so the necessary series resistance should be 2 k w . input offset voltage nulling the opx81 family of op amps was designed for low offset voltages less than 1 mv. the single OP181 does provide two offset adjust terminals, should the user require greater precision. in general, these terminals should be used only to zero amplifier offsets and should not be used to adjust system offset voltages. a 20 k w potentiometer connected to the offset adjust terminals, with the wiper connected to v ee , can be used to reduce the offset voltage of the amplifier. the OP181 should be connected in the unity-gain configuration (as shown in figure 33) or in a gain configuration. the potentiometer should be adjusted until v out is minimized. the wiper of the potentiometer must be connected to v ee ; connecting it to the positive supply rail could damage the device. 6 5 7 4 1 2 3 +5v OP181 v out 20k w pot. v ee = ?v figure 33. offset voltage nulling circuit input common-mode voltage range the opx81 is rated with an input common-mode voltage range from v ee to 1 volt under v cc . however, the op amp can still operate even with a common-mode voltage that is slightly less than v ee . figure 34 shows an OP181 configured as a difference amplifier with a single supply voltage of +3 v. negative dc voltages are applied at both input terminals creating a common- mode voltage that is less than ground. a 400 mv p-p input signal is then applied to the noninverting input. figure 35 shows a picture of the input and output waves. notice how the output of the amplifier also drops slightly negative without distortion. OP181 v out +3v 100k w 100k w 100k w 100k w v in = 1khz at 400mv p-p ?.1v ?.27v figure 34. OP181 configured as a difference amplifier operating at v cm < 0 v
OP181/op281/op481 C11C rev. 0 10 0% 100 90 0.2ms 0.1v 0v v in v out figure 35. input and output signals with v cm < 0 v overdrive recovery time the amount of time it takes for an amplifier to recover from saturation can be an important consideration when using an amplifier as a comparator or when outputs can be driven to the supplies. the overdrive recovery time for the OP181 is 50 m s with the amplifier running from a 3 volt supply and increases to 100 m s with a 10 volt supply. figure 36 shows the result of the OP181 running from a 3 v supply with its output being overdriven. 10 0% 100 90 0.2ms 0.1v v s = +3v a v = +100 v in scale 0.1v 0v v out scale 1v 0v figure 36. output of the op amp recovering from saturation capacitive loading most low supply current amplifiers have difficulty driving capacitive loads due to the higher currents required from the output stage for such loads. higher capacitance at the output will increase the amount of overshoot and ringing in the amplifiers step response and could even affect the stability of the device. however, through careful design of the output stage and its high phase margin, the opx81 family can tolerate some degree of capacitive loading. figure 37 shows the step response of an OP181 with a 10 nf capacitor connected at the output. notice that the overshoot of the output does not exceed more than 10% with such a load, even with a supply voltage of only +3 v. 10 0% 100 90 figure 37. ringing and overshoot of the output of the amplifier a micropower reference voltage generator many single supply circuits are configured with the circuit biased to 1/2 of the supply voltage. in these cases, a false- ground reference can be created by using a voltage divider buffered by an amplifier. figure 38 shows the schematic for such a circuit. the two 1 m w resistors generate the reference voltage while drawing only 1.5 m a of current from a 3 v supply. a capacitor connected from the inverting terminal to the output of the op amp provides compensation to allow for a bypass capacitor to be connected at the reference output. this bypass capacitor helps establish an ac ground for the reference output. the entire reference generator draws less than 5 m a from a 3 v supply source. 6 7 4 2 3 OP181 10k w 0.022? v ref +1.5v to +6v 1? 1? 1m w +3v to +12v 100 w 1m w figure 38. a micropower bias voltage generator a window comparator the extremely low power supply current demands of the opx81 family make it ideal for use in long life battery powered applica- tions such as a monitoring system. figure 39 shows a circuit that uses the op281 as a window comparator.
OP181/op281/op481 C12C rev. 0 a1 r1 r2 +3v op281-a v in 2k w 5.1k w +3v +3v v out q1 5.1k w v h d1 10k w a2 r3 r4 +3v +3v v l d2 op281-b figure 39. using the op281 as a window comparator the threshold limits for the window are set by v h and v l , provided that v h > v l . the output of a1 will stay at the negative rail, in this case ground, as long as the input voltage is less than v h . similarly, the output of a2 will stay at ground as long the input voltage is higher than v l . as long as v in remains between v l and v h , the outputs of both op amps will be 0 v. with no current flowing in either d1 or d2, the base of q1 will stay at ground, putting the transistor in cutoff and forcing v out to the positive supply rail. if the input voltage rises above v h , the output of a2 stays at ground, but the output of a1 will go to the positive rail, and d1 will conduct current. this creates a base voltage that will turn on q1 and drive v out low. the same condition occurs if v in falls below v l with a2s output going high, and d2 conducting current. therefore, v out will be high if the input voltage is between v l and v h , and v out will be low if the input voltage moves outside of that range. the r1 and r2 voltage divider sets the upper window voltage, and the r3 and r4 voltage divider sets the lower voltage for the window. for the window comparator to function properly, v h must be a greater voltage than v l . v h = r 2 r 1 + r 2 v l = r 4 r 3 + r 4 the 2 k w resistor connects the input voltage to the input termi- nals to the op amps. this protects the op281 from possible excess current flowing into the input stages of the devices. d1 and d2 are small-signal switching diodes (1n4446 or equiva- lent), and q1 is a 2n2222 or equivalent npn transistor. a low-side current monitor in the design of power supply control circuits, a great deal of design effort is focused on ensuring a pass transistors long-term reliability over a wide range of load current conditions. as a result, monitoring and limiting device power dissipation is of prime importance in these designs. figure 40 shows an example of a +5 v, single-supply current monitor that can be incorpo- rated into the design of a voltage regulator with fold-back current limiting or a high current power supply with crowbar protection. the design capitalizes on the OP181s common- mode range that extends to ground. current is monitored in the power supply return path where a 0.1 w shunt resistor, r sense , creates a very small voltage drop. the voltage at the inverting terminal becomes equal to the voltage at the noninverting terminal through the feedback of q1, which is a 2n2222 or equivalent npn transistor. this makes the voltage drop across r1 equal to the voltage drop across r sense . therefore, the current through q1 becomes directly proportional to the current through r sense , and the output voltage is given by: v out = v ee - r 2 r 1 r sense i l ? ? ? ? the voltage drop across r2 increases with i l increasing, so v out decreases with higher supply current being sensed. for the element values shown, the v out transfer characteristic is C2.5 v/a, decreasing from v ee . +5v return to ground OP181 +5v r2 2.49k w v out r1 100 w 0.1 w r sense q1 figure 40. a low-side load current monitor low voltage half-wave and full-wave rectifiers because of its quick overdrive recovery time, an op281 can be configured as a full-wave rectifier for low frequency (<500 hz) applications. figure 41 shows the schematic. +3v op281-a v in = 2v p-p 2k w a1 +3v op281-b a2 r1 = 100k w r2 = 100k w full-wave rectified output half-wave rectified output figure 41. single supply full- and half-wave rectifiers using an op281 10 0% 100 90 scale 0.1v/div scale 0.1ms/div figure 42. full-wave rectified signal
OP181/op281/op481 C13C rev. 0 amplifier a1 is used as a voltage follower that will only track the input voltage when it is greater than 0 v. this provides a half- wave rectification of the input signal to the noninverting terminal of amplifier a2. when a1s output is following the input, the inverting terminal of a2 will also follow the input from the virtual ground between the inverting and noninverting terminals of a2. with no potential difference across r1, no current flows through either r1 or r2, therefore the output of a2 will also follow the input. now, when the input voltage goes below 0 v, the noninverting terminal of a2 becomes 0 v. this makes a2 work as an inverting amplifier with a gain of 1 and provides a full-wave rectified version of the input signal. a 2 k w resistor in series with a1s noninverting input protects the device when the input signal becomes less than ground. a battery powered telephone headset amplifier figure 43 shows how the op281 can be used as a two-way amplifier in a telephone headset. one side of the op281 can be used as an amplifier for the microphone, while the other side can be used to drive the speaker. a typical telephone headset uses a 600 w speaker and an electret microphone that requires a supply voltage and a biasing resistor. +3v op281-b 20k w 20k w q1 q2 +3v 1? 600 w speaker 50k w 10k w 1? 10k w pot. +3v 1m w 1m w 1? 1? input 1m w +3v op281-a 11k w 300k w 0.1? 1? +3v 1m w 1? mic out 2.2k w +3v electret mic figure 43. a battery powered telephone headset two-way amplifier the op281-a op amp provides about 29 db of gain for audio signals coming from the microphone. the gain is set by the 300 k w and 11 k w resistors. the gain bandwidth product of the amplifier is 95 khz, which, for the set gain of 28, yields a C3 db rolloff at 3.4 khz. this is acceptable since telephone audio is band limited for 300 khz to 3 khz signals. if higher gain is required for the microphone, an additional gain stage should be used, as adding any more gain to the op281 would limit the audio bandwidth. a 2.2 k w resistor is used to bias the electret microphone. this resistor value may vary depending on the specifications on the microphone being used. the output of the microphone is ac coupled to the noninverting terminal of the op amp. two 1 m w resistors are used to provide the dc offset for single supply use. the op281-b amplifier can provide up to 15 db of gain for the headset speaker. incoming audio signals are ac coupled to a 10 k w potentiometer that is used to adjust the volume. again, two 1 m w resistors provide the dc offset with a 1 m f capacitor establishing an ac ground for the volume control potentiometer. because the op281 is a rail-to-rail output amplifier, it would have difficulty driving a 600 w speaker directly. here, a class ab buffer is used to isolate the load from the amplifier and also provide the necessary current drive to the speaker. by placing the buffer in the feedback loop of the op amp, crossover distortion can be minimized. q1 and q2 should have minimum betas of 100. the 600 w speaker is ac coupled to the emitters to prevent any quiescent current from flowing in the speaker. the 1 m f coupling capacitor makes an equivalent high pass filter cutoff at 265 hz with a 600 w load attached. again, this does not pose a problem, as it is outside the frequency range for telephone audio signals. the circuit in figure 43 draws around 250 m a of current. the class ab buffer has a quiescent current of 140 m a while roughly 100 m a is drawn by the microphone itself. a cr2032 3 v lithium battery has a life expectancy of 160 ma hours, which means this circuit could run continuously for 640 hours on a single battery. spice macro-model * OP181 spice macro-model * 9/96, ver. 1 * * copyright 1996 by analog devices * * refer to readme.doc file for license statement. use of this * model indicates your acceptance of the terms and provisions in * the license statement. * * node assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output *|| | | | *|| | | | .subckt OP181 1 2 99 50 45 * * input stage * q1 413pix q2 675pix i1 99 8 1.28e-6 eos 7 2 poly(1) (12, 98) 80e-6 1 ios 1 2 1e-10 rc1 4 50 500e3 rc2 6 50 500e3 re1 3 8 108 re2 5 8 108 v1 99 13 dc .9 v2 99 14 dc .9 d1 3 13 dx d2 5 14 dx * * cmrr 76db, zero at 1khz *
OP181/op281/op481 C14C rev. 0 ecm1 11 98 poly(2) (1, 98) (2, 98) 0 .5 .5 r1 11 12 1.59e6 c1 11 12 100e-12 r2 12 98 283 * * pole at 900khz * eref 98 0 (90, 0) 1 g1 98 20 (4, 6) 1e-6 r3 20 98 1e6 c2 20 98 177e-15 * * pole at 500khz * e2 21 98 (20, 98) 1 r4 21 22 1e6 c3 22 98 320e-15 * * gain stage * cf 45 40 8. 5e-12 r5 40 98 65. 65e6 g3 98 40 (22, 98) 4.08e-7 d3 40 41 dx d4 42 40 dx v3 99 41 dc 0.5 v4 42 50 dc 0.5 * * output stage * isy 99 50 1.375e-6 rs1 99 90 10e6 rs2 90 50 10e6 m1 45 46 99 99 pox l=1.5u w=300u m2 45 47 50 50 nox l=1.5u w=300u eg1 99 46 poly(1) (98, 40) 0.77 1 eg2 47 50 poly(1) (40, 98) 0.77 1 * * models * .model pox pmos (level=2, kp=25e-6, vto=-0.75, lambda=0.01) .model nox nmos (level=2, kp=25e-6, vto=0.75, lambda=0.01) .model pix pnp (bf=200) .model dx d(is=1e-14) .ends
OP181/op281/op481 C15C rev. 0 14-lead plastic dip (n-14) 14 17 8 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) pin 1 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 14-lead narrow body soic (so-14) 14 8 7 1 0.3444 (8.75) 0.3367 (8.55) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 14-lead tssop (ru-14) 14 8 7 1 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 outline dimensions dimensions shown in inches and (mm). 8-lead plastic dip (n-8) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-lead soic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 8-lead tssop (ru-8) 8 5 4 1 0.122 (3.10) 0.114 (2.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.0256 (0.65) bsc seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0
c2195C12C10/96 printed in u.s.a. C16C

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